There is a continuing trend to employ and/or fabricate advanced integrated circuits using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. In one conventional technique, a memory cell of a semiconductor memory device having one or more memory transistors may be read by applying a bias to a drain region of a memory transistor, as well as a bias to a gate of the memory transistor that is above a threshold voltage of the memory transistor. As such, conventional reading techniques sense an amount of channel current provided/generated in response to the application of the bias to the gate of the memory transistor to determine a state of the memory cell. For example, an electrically floating body region of the memory cell may have two or more different current states corresponding to two or more different logical states (e.g., two different current conditions/states corresponding to two different logic states: binary “0” data state and binary “1” data state).
Also, conventional writing techniques for memory cells having an N-Channel type memory transistor typically result in an excess of majority charge carriers by channel impact ionization or by band-to-band tunneling (gate-induced drain leakage “GIDL”). The majority charge carriers may be removed via drain side hole removal, source side hole removal, or drain and source hole removal, for example, using back gate pulsing.
Often, conventional reading and/or writing techniques may lead to relatively large power consumption and large voltage swings which may cause disturbance to memory cells on unselected rows in the memory device. Also, pulsing between positive and negative gate biases during read and write operations may reduce a net quantity of charge carriers in a body region of a memory cell in the semiconductor memory device, which, in turn, may gradually eliminate data stored in the memory cell. In the event that a negative voltage is applied to a gate of a memory cell transistor, thereby causing a negative gate bias, a channel of minority charge carriers beneath the gate may be eliminated. However, some of the minority charge carriers may remain “trapped” in interface defects. Some of the trapped minority charge carriers may recombine with majority charge carriers, which may be attracted to the gate, and the net charge in majority charge carriers located in the floating body region may decrease over time. This phenomenon may be characterized as charge pumping, which is a problem because the net quantity of charge carriers may be reduced in the memory cell, which, in turn, may gradually eliminate data stored in the memory cell.
Additionally, conventional reading and/or writing techniques may lead to disturbance (e.g., influence a data state stored in a memory cell) in one or more unselected memory cells. For example, a plurality of memory cells may be coupled to a common source line (SL). Although, a single memory cell may be selected for a read and/or a write operations, all memory cells coupled to the source line (SL) may receive a voltage applied to the source line (SL). Therefore, one or more unselected memory cells coupled to the source line (SL) may be disturbed (e.g., influence an amount of charged stored in the memory cells) by a voltage applied to the source line (SL).
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for reading from and/or writing to semiconductor memory devices.